The present invention relates to a semiconductor memory device and, more particularly, to a delay locked loop circuit for controlling an internal operation of a semiconductor memory device in order that data are outputted in synchronization with a system clock based on an external command.
In a system including a plurality of semiconductor devices, the semiconductor memory device stores data. When a data processing unit, i.e., a CPU, requires data, the semiconductor memory device outputs data corresponding to an address inputted from the data processing unit or stores data provided from the data processing unit in a cell position corresponding to the address.
With the increase in the operating speed of a system having semiconductor devices and the development of semiconductor integrated crictui technology, the semiconductor memory device is required to output or store data faster than before. In order to input/output data at high speed, a synchronous memory device, which is capable of inputting/outputting data in synchronization with a system clock inputted from the external circuit, has been developed. However, since the synchronous memory device did not sufficiently satisfy the required speed of inputting/outputting data, a DDR (Double Data Rate) synchronous memory device, which is capable of inputting/outputting data at a rising edge and a falling edge of a system clock, respectively, has been developed.
Since the DDR synchronous memory device should input/output data at the rising edge and the falling edge of the system clock, respectively, it should process two data within one time period of the system clock. That is, the DDR synchronous memory device should output data or receive and store data at the rising edge and the falling edge of the system clock, respectively. Particularly, a timing at which the DDR synchronous memory device outputs data should accurately synchronize with the rising edge or the falling edge of the system clock. Thus, a data output circuit within the DDR synchronous memory device is used to control an internal output and a transfer timing of data so that the data are outputted in synchronization with the rising edge and the falling edge of the inputted system clock.
However, the system clock inputted to the semiconductor memory device is inevitably delayed by a clock input buffer disposed in the semiconductor memory device and a transmission line for transferring a clock to the data output circuit. Thus, if the data output circuit outputs data in synchronization with the system clock which is transmitted with a delay time, an external apparatus receives output data which are not in synchronization with the rising edge and the falling edge of the system clock.
In order to solve such a problem, the semiconductor memory device includes a delay locked loop circuit for compensating for the delay of the clock and fixing the phase of an internal clock. The delay locked loop circuit compensates for a value of the delay caused by an internal circuit within the semiconductor memory device until the system clock is inputted to the semiconductor memory device to be transferred to the data output circuit. The delay locked loop circuit finds out a time at which the system clock is delayed by the clock input buffer within the semiconductor memory device and the transmission line for transferring the clock, and delays the system clock corresponding to the found value to output the system clock to the data output circuit. That is, through the delay locked loop circuit, the system clock inputted to the semiconductor memory device is transferred to the data output circuit as the internal clock having the fixed delay value. When the data output circuit outputs data in synchronization with the system clock having the fixed delay value, it is determined by the external circuit that the data are accurately in synchronization with the system clock to be outputted.
Actually, a delay locked clock outputted from the delay locked loop circuit is transferred to an output buffer at a timing which precedes a data output timing by one time period, and the data are in synchronization with the transferred delay locked clock to be outputted. Thus, the system clock outputs the data quickly as much as it is delayed by the internal circuit within the semiconductor memory device. Therefore, it is determined by the external circuit of the semiconductor memory device that the data are accurately in synchronization with the rising edge and the falling edge of the system clock inputted to the semiconductor memory device and outputted. Accordingly, the delay locked loop circuit finds out how quickly the data should be outputted to compensate for the delay value of the system clock within the semiconductor memory device.
The conventional delay locked loop circuit compares the phase of the system clock with that of the internal clock reflecting the delay value and controls the phases through a delay line which includes unit delay cells having a constant delay time that is as much as the sensed phase difference. However, it is difficult to use the conventional delay locked loop circuit in a semiconductor memory device which operates at a high-frequency.
Recently, since the semiconductor memory device is required to operate at a high speed, the frequency of the system clock inputted to the semiconductor memory device becomes high. Also, a semiconductor memory device in which the number of the data outputted for one time period of the system clock is increased from two to four, has been newly suggested. The semiconductor memory device operating at high speed uses, as a reference for inputting/outputting data, a separate data clock which has a frequency twice as high as that of the system clock. For example, if the frequency of the system clock, which is a reference for inputting/outputting a command and an address, is 1 GHz, the frequency of the data clock is 2 GHz. In order for the semiconductor memory device to operate in response to such a high-frequency clock, the conventional delay locked loop circuit, which compensates for the delay value of the system clock to control the timing at which the data are outputted from the inside to the external circuit, should minutely and accurately control the change in the delay value that is used to control phase locking, as the clock frequency becomes high.
The conventional delay locked loop circuit detects a phase difference between an inputted clock and a reference clock, controls a delay element to reduce the phase difference, delays the clock by delay model which is occurred during the process of inputting/outputting the clock, and performs a feedback operation of the delayed clock. In each of the above mentioned processes of the delay locked loop circuit using a negative delay effect, a delay value change or a clock distortion can occur because of the change in surrounding environments, such as a voltage level, a temperature, a pressure and a process in the semiconductor memory device. As the frequencies of the inputted clock and the reference clock become high, the distortion, error and delay value change in each process should be considered as important factors in a time domain, and the phase locking based on the distortion, error and delay value change becomes more difficult. Accordingly, the conventional analogue method, which removes the phase difference by continuously tracking the phase of the clock through the control of the delay value between the inputted clock and the reference clock, should be improved.